Non-volatile data storage devices, such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase a storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
Error correction coding (ECC) is often used to correct errors that occur in data read from a memory device. Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g. “parity bits”) that may be stored with the data as an ECC codeword. As more parity bits are used, an error correction capacity of the ECC increases and a number of bits required to store the encoded data also increases.
One source of errors that occur in data stored in a memory device is a result of repeated write/erase (W/E) cycles to the memory device. Cell threshold voltage distributions (CVDs) may shift and broaden with increasing numbers of W/E cycles, resulting in an increasing number of data errors as the memory device ages. Wear leveling techniques may be used to distribute W/E operations so that all regions of the memory are subjected to approximately an equal number of W/E cycles. As a result, wear leveling may extend a useful life of the memory device that may otherwise be limited by a portion of the memory that experiences accelerated wearing due to more frequent erase operations as compared to other portions of the memory.
Erasing a block of flash memory conventionally includes applying an erase voltage to the erase block, removing the erase voltage, and reading the storage elements of the block. Erasing a cell conventionally is performed by removing charge from an insulated floating gate of a transistor. As charge is repeatedly applied to the floating gate through via the insulting material (to program data into the cell) and later removed from the floating gate via the insulating material (to erase the data from the cell), programming and erase performance of the transistor may degrade due to changes in the electrical properties of the insulating material. Storage elements that experience a relatively large number of cell erases (e.g., cells that are repeatedly programmed to store a “0” value and then erased) experience more wear than storage elements that have experienced a relatively small number of cell erases (e.g., cells that frequently remain in the erase state to store a “1” value), over an equal number of W/E cycles.